`include "defines.v"
module data_ram(
	input wire clk,
	input wire ram_ce,
	input wire[31:0] addr,
	input wire[31:0] wdata,
	input wire write_ce,
	input wire[3:0] sel, //字节选择信号
	output reg[31:0] rdata
);
	reg[7:0] data_mem0[`DataMemCapacity-1:0];
	reg[7:0] data_mem1[`DataMemCapacity-1:0];
	reg[7:0] data_mem2[`DataMemCapacity-1:0];
	reg[7:0] data_mem3[`DataMemCapacity-1:0];
	//读
	always@(*)
		if(ram_ce == `RamDisable)
			rdata = `ZeroWord;
		else
			rdata = {data_mem3[addr[`DataMemAddrWidth-1:2]],
					data_mem2[addr[`DataMemAddrWidth-1:2]],
					data_mem1[addr[`DataMemAddrWidth-1:2]],
					data_mem0[addr[`DataMemAddrWidth-1:2]]};
	//写
	always@(posedge clk)
		if(ram_ce == `RamEnable && write_ce == `WriteEnable)
		begin
			if(sel[3] == 1'b1)
				data_mem3[addr[`DataMemAddrWidth-1:2]] <= wdata[31:24];
			if(sel[2] == 1'b1)
				data_mem2[addr[`DataMemAddrWidth-1:2]] <= wdata[23:16];
			if(sel[1] == 1'b1)
				data_mem1[addr[`DataMemAddrWidth-1:2]] <= wdata[15:8];
			if(sel[0] == 1'b1)
				data_mem0[addr[`DataMemAddrWidth-1:2]] <= wdata[7:0];
			
		end
endmodule
